Onder, Sebastian; Gaggl, Philipp; Burin, Jürgen; Gsponer, Andreas; Knopf, Matthias; Waid, Simon; Moffat, Neil; Pellegrini, Giulio; Bergauer, Thomas
Design and simulation of a 4H-SiC low gain avalanche diode with trench-isolation Journal Article
In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 1080, pp. 170740, 2025, ISSN: 0168-9002.
@article{ONDER2025170740,
title = {Design and simulation of a 4H-SiC low gain avalanche diode with trench-isolation},
author = {Sebastian Onder and Philipp Gaggl and Jürgen Burin and Andreas Gsponer and Matthias Knopf and Simon Waid and Neil Moffat and Giulio Pellegrini and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2025/06/OGBGKWMPB25_NIMA.pdf},
doi = {https://doi.org/10.1016/j.nima.2025.170740},
issn = {0168-9002},
year = {2025},
date = {2025-01-01},
urldate = {2025-01-01},
journal = {Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment},
volume = {1080},
pages = {170740},
abstract = {We present the design and simulation of a 30µm thick 4H-SiC Low Gain Avalanche Diode (LGAD) optimized for high-voltage operation. A 2.4µm thick epitaxially grown gain layer enables controlled internal amplification up to 1kV reverse bias, while maintaining full depletion below 500V. Electrical characteristics, including I-V, C-V, and gain behavior, were simulated in Synopsys Sentaurus Technology Computer-Aided Design (TCAD) using a quasi-1D geometry and verified across process-related variations in gain layer parameters. To ensure high-voltage stability and proper edge termination, a guard structure combining deep etched trenches and deep p+ junction termination extension (JTE) implants was designed. TCAD simulations varying the guard structure dimensions yielded an optimized design with a breakdown voltage above 2.4kV. A corresponding wafer run is currently processed at IMB-CNM, Barcelona.},
keywords = {High-energy physics, LGAD, Low gain avalanche diode, Particle detector, Silicon carbide, TCAD},
pubstate = {published},
tppubtype = {article}
}
We present the design and simulation of a 30µm thick 4H-SiC Low Gain Avalanche Diode (LGAD) optimized for high-voltage operation. A 2.4µm thick epitaxially grown gain layer enables controlled internal amplification up to 1kV reverse bias, while maintaining full depletion below 500V. Electrical characteristics, including I-V, C-V, and gain behavior, were simulated in Synopsys Sentaurus Technology Computer-Aided Design (TCAD) using a quasi-1D geometry and verified across process-related variations in gain layer parameters. To ensure high-voltage stability and proper edge termination, a guard structure combining deep etched trenches and deep p+ junction termination extension (JTE) implants was designed. TCAD simulations varying the guard structure dimensions yielded an optimized design with a breakdown voltage above 2.4kV. A corresponding wafer run is currently processed at IMB-CNM, Barcelona.
Burin, Jürgen; Gaggl, Philipp; Waid, Simon; Gsponer, Andreas; Bergauer, Thomas
TCAD Parameters for 4H-SiC: A Review Miscellaneous ForthcomingOpen Access
Forthcoming.
BibTeX |
@misc{burin2024tcadparameters4hsicreview,
title = {TCAD Parameters for 4H-SiC: A Review},
author = {Jürgen Burin and Philipp Gaggl and Simon Waid and Andreas Gsponer and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2025/12/4H-SiC_Review.pdf
https://arxiv.org/abs/2410.06798},
doi = {10.48550/arXiv.2410.06798},
year = {2025},
date = {2025-07-01},
urldate = {2025-07-01},
booktitle = {TCAD Parameters for 4H-SiC: A Review},
keywords = {featured, OpenAccess},
pubstate = {forthcoming},
tppubtype = {misc}
}
Waid, Simon; Gaggl, Philipp; Gsponer, Andreas; Thalmeier, Richard; Burin, Jürgen; Knopf, Matthias; Bergauer, Thomas
From single particles to clinical beam rates: A wide dynamic range beam monitor Journal Article
In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 1080, pp. 170674, 2025, ISSN: 0168-9002.
@article{WAID2025170674,
title = {From single particles to clinical beam rates: A wide dynamic range beam monitor},
author = {Simon Waid and Philipp Gaggl and Andreas Gsponer and Richard Thalmeier and Jürgen Burin and Matthias Knopf and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2025/06/2504.17466v1.pdf
https://arxiv.org/abs/2504.17466},
doi = {https://doi.org/10.1016/j.nima.2025.170674},
issn = {0168-9002},
year = {2025},
date = {2025-01-01},
urldate = {2025-01-01},
journal = {Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment},
volume = {1080},
pages = {170674},
abstract = {Access to high-energy particle beams is key for testing high-energy physics (HEP) instruments. Accelerators for cancer treatment can serve as such a testing ground. However, HEP instrument tests typically require particle fluxes significantly lower than cancer treatment. Thus, facilities need adaptations to fulfill both the requirements for cancer treatment and the requirements for HEP instrument testing. We report on the progress made in developing a beam monitor with a sufficient dynamic range to allow for the detection of single particles, while still being able to act as a monitor at the clinical particle rates of the MedAustron treatment facility. The beam monitor is designed for integration into existing accelerators.},
keywords = {Beam Monitor, High-dynamic-range, Medical accelerator},
pubstate = {published},
tppubtype = {article}
}
Access to high-energy particle beams is key for testing high-energy physics (HEP) instruments. Accelerators for cancer treatment can serve as such a testing ground. However, HEP instrument tests typically require particle fluxes significantly lower than cancer treatment. Thus, facilities need adaptations to fulfill both the requirements for cancer treatment and the requirements for HEP instrument testing. We report on the progress made in developing a beam monitor with a sufficient dynamic range to allow for the detection of single particles, while still being able to act as a monitor at the clinical particle rates of the MedAustron treatment facility. The beam monitor is designed for integration into existing accelerators.
Gaggl, Philipp; Burin, Jürgen; Gsponer, Andreas; Waid, Simon-Emanuel; Thalmeier, Richard; Bergauer, Thomas
TCAD modeling of radiation-induced defects in 4H-SiC diodes Journal Article Open Access
In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 1070, pp. 170015, 2025, ISSN: 0168-9002.
@article{GAGGL2025170015,
title = {TCAD modeling of radiation-induced defects in 4H-SiC diodes},
author = {Philipp Gaggl and Jürgen Burin and Andreas Gsponer and Simon-Emanuel Waid and Richard Thalmeier and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2025/05/GBGWTB24_NIMA.pdf
https://arxiv.org/abs/2407.11776},
doi = {https://doi.org/10.1016/j.nima.2024.170015},
issn = {0168-9002},
year = {2025},
date = {2025-01-01},
urldate = {2025-01-01},
journal = {Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment},
volume = {1070},
pages = {170015},
abstract = {4H silicon carbide (SiC) has several advantageous properties compared to silicon (Si) making it an appealing detector material, such as a larger charge carrier saturation velocity, bandgap, and thermal conductivity. While the current understanding of material and model parameters suffices to simulate unirradiated 4H-SiC using TCAD software, configurations accurately predicting performance degradation after high levels of irradiation due to induced traps and recombination centers do not exist. Despite increasing efforts to characterize the introduction and nature of such defects, published results are often contradictory. This work presents a bulk radiation damage model for TCAD simulation based on existing literature and optimized on measurement results of neutron-irradiated 4H-SiC pad diodes. Experimentally observed effects, such as flattening of the detector capacitance, loss of rectification properties, and degradation in charge collection efficiency, are reproduced. The EH4 center is suggested as a major lifetime killer in 4H-SiC, while the still controversial assumption of the EH6,7 deep-level being of donor type is reinforced.},
keywords = {Defect states, Numerical simulations, OpenAccess, Radiation damage to detector materials (solid state), Silicon carbide, TCAD},
pubstate = {published},
tppubtype = {article}
}
4H silicon carbide (SiC) has several advantageous properties compared to silicon (Si) making it an appealing detector material, such as a larger charge carrier saturation velocity, bandgap, and thermal conductivity. While the current understanding of material and model parameters suffices to simulate unirradiated 4H-SiC using TCAD software, configurations accurately predicting performance degradation after high levels of irradiation due to induced traps and recombination centers do not exist. Despite increasing efforts to characterize the introduction and nature of such defects, published results are often contradictory. This work presents a bulk radiation damage model for TCAD simulation based on existing literature and optimized on measurement results of neutron-irradiated 4H-SiC pad diodes. Experimentally observed effects, such as flattening of the detector capacitance, loss of rectification properties, and degradation in charge collection efficiency, are reproduced. The EH4 center is suggested as a major lifetime killer in 4H-SiC, while the still controversial assumption of the EH6,7 deep-level being of donor type is reinforced.
Burin, Jürgen; Hahn, Christopher; Gaggl, Philipp; Gsponer, Andreas; Waid, Simon; Bergauer, Thomas
TCAD simulations of radiation damage in 4H-SiC Journal Article
In: Microelectronic Engineering, vol. 299, pp. 112352, 2025, ISSN: 0167-9317.
@article{BURIN2025112352,
title = {TCAD simulations of radiation damage in 4H-SiC},
author = {Jürgen Burin and Christopher Hahn and Philipp Gaggl and Andreas Gsponer and Simon Waid and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2025/05/BHGGWB25_MEE.pdf},
doi = {https://doi.org/10.1016/j.mee.2025.112352},
issn = {0167-9317},
year = {2025},
date = {2025-01-01},
urldate = {2025-01-01},
journal = {Microelectronic Engineering},
volume = {299},
pages = {112352},
abstract = {In this paper we present simulation based radiation damage modeling of 4H silicon carbide (SiC) using the technology computer aided design (TCAD) tools for up to 1 kV forward and backward bias. After verifying the TCAD framework from Global TCAD Solutions (GTS) against Sentaurus simulations for silicon we use it to approximate measurements of neutron-irradiated 4H-SiC particle detectors, i.e., pin-diodes. Based on our simulations we are not only able to evaluate the accuracy of the predictions but also to provide an explanation for the almost negligible current of radiated devices under high forward bias.},
keywords = {Particle detector},
pubstate = {published},
tppubtype = {article}
}
In this paper we present simulation based radiation damage modeling of 4H silicon carbide (SiC) using the technology computer aided design (TCAD) tools for up to 1 kV forward and backward bias. After verifying the TCAD framework from Global TCAD Solutions (GTS) against Sentaurus simulations for silicon we use it to approximate measurements of neutron-irradiated 4H-SiC particle detectors, i.e., pin-diodes. Based on our simulations we are not only able to evaluate the accuracy of the predictions but also to provide an explanation for the almost negligible current of radiated devices under high forward bias.
Gsponer, Andreas; Gaggl, Philipp; Burin, Jürgen; Waid, Simon; Bergauer, Thomas
Observation of Charge Enhancement in Forward-Biased Neutron-Irradiated 4H-SiC PiN Detectors in UV-TCT Measurements Proceedings Article Open Access
In: Proceedings of Technology & Instrumentation in Particle Physics — PoS(TIPP2023), pp. 103, Sissa Medialab, Cape Town, Western Cape, South Africa, 2025.
BibTeX |
@inproceedings{gsponer2025,
title = {Observation of Charge Enhancement in Forward-Biased Neutron-Irradiated 4H-SiC PiN Detectors in UV-TCT Measurements},
author = {Andreas Gsponer and Philipp Gaggl and Jürgen Burin and Simon Waid and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2025/06/TIPP2023_103.pdf
https://arxiv.org/abs/2412.06973},
doi = {10.22323/1.468.0103},
year = {2025},
date = {2025-04-01},
urldate = {2025-04-01},
booktitle = {Proceedings of Technology & Instrumentation in Particle Physics — PoS(TIPP2023)},
pages = {103},
publisher = {Sissa Medialab},
address = {Cape Town, Western Cape, South Africa},
keywords = {OpenAccess},
pubstate = {published},
tppubtype = {inproceedings}
}
Waid, Simon; Gsponer, Andreas; Burin, Jürgen; Gaggl, Philipp; Thalmeier, Richard; Bergauer, Thomas
SiC based beam monitoring system for particle rates from kHz to GHz Journal Article
In: Journal of Instrumentation, vol. 19, no. 04, pp. C04055, 2024.
@article{WGMPTB24:JoI,
title = {SiC based beam monitoring system for particle rates from kHz to GHz},
author = {Simon Waid and Andreas Gsponer and Jürgen Burin and Philipp Gaggl and Richard Thalmeier and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2024/04/WGMPTB24_JoI.pdf
https://arxiv.org/abs/2310.14996},
doi = {10.1088/1748-0221/19/04/C04055},
year = {2024},
date = {2024-04-01},
urldate = {2024-04-01},
journal = {Journal of Instrumentation},
volume = {19},
number = {04},
pages = {C04055},
publisher = {IOP Publishing},
abstract = {The extremely low dark current of silicon carbide (SiC) detectors, even after high-fluence irradiation, was utilized to develop a beam monitoring system for a wide range of particle rates, i.e., from the kHz to the GHz regime. The system is completely built from off-the-shelf components and is focused on compactness and simple deployment. Beam tests using a 50 um thick SiC detector reveal, that for low fluences, single particles can be detected and counted. For higher fluences, beam properties were extracted from beam cross sections using a silicon strip detector. Overall, accurate results were achieved up to a particle rate of 109 particles per second.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
The extremely low dark current of silicon carbide (SiC) detectors, even after high-fluence irradiation, was utilized to develop a beam monitoring system for a wide range of particle rates, i.e., from the kHz to the GHz regime. The system is completely built from off-the-shelf components and is focused on compactness and simple deployment. Beam tests using a 50 um thick SiC detector reveal, that for low fluences, single particles can be detected and counted. For higher fluences, beam properties were extracted from beam cross sections using a silicon strip detector. Overall, accurate results were achieved up to a particle rate of 109 particles per second.
Gsponer, Andreas; Knopf, Matthias; Gaggl, Philipp; Burin, Jürgen; Waid, Simon; Bergauer, Thomas
Measurement of the electron–hole pair creation energy in a 4H-SiC p-n diode Journal Article Open Access
In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, pp. 169412, 2024, ISSN: 0168-9002.
@article{GSPONER2024169412,
title = {Measurement of the electron–hole pair creation energy in a 4H-SiC p-n diode},
author = {Andreas Gsponer and Matthias Knopf and Philipp Gaggl and Jürgen Burin and Simon Waid and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2024/05/GKGBWB24_NIMA.pdf
https://arxiv.org/abs/2311.03902},
doi = {https://doi.org/10.1016/j.nima.2024.169412},
issn = {0168-9002},
year = {2024},
date = {2024-01-01},
urldate = {2024-01-01},
journal = {Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment},
pages = {169412},
abstract = {For 4H silicon carbide (4H-SiC), the values for the electron–hole pair creation energy ϵi published in the literature vary significantly. This work presents an experimental determination of ϵi using 50 μm 4H-SiC p-n diodes designed for particle detection in high-energy physics. The detector response was measured for α particles between 4.2MeV and 5.6MeV for 4H-SiC and a silicon reference device. Different α energies were obtained by using multiple nuclides and varying the effective air gap between the α source and the detector. The energy deposited in the detectors was determined using a Monte Carlo simulation, taking into account the device cross-sections. A linear fit of the detector response to the deposited energy yields ϵi=(7.83±0.02)eV, which agrees well with the most recent literature. For the 4H-SiC detectors, a linewidth of 28keV FWHM was achieved, corresponding to an energy resolution of 0.5%.},
keywords = {4H-SiC, Electron–pair creation energy, OpenAccess, Planar diode, Silicon carbide, Wide-bandgap detector},
pubstate = {published},
tppubtype = {article}
}
For 4H silicon carbide (4H-SiC), the values for the electron–hole pair creation energy ϵi published in the literature vary significantly. This work presents an experimental determination of ϵi using 50 μm 4H-SiC p-n diodes designed for particle detection in high-energy physics. The detector response was measured for α particles between 4.2MeV and 5.6MeV for 4H-SiC and a silicon reference device. Different α energies were obtained by using multiple nuclides and varying the effective air gap between the α source and the detector. The energy deposited in the detectors was determined using a Monte Carlo simulation, taking into account the device cross-sections. A linear fit of the detector response to the deposited energy yields ϵi=(7.83±0.02)eV, which agrees well with the most recent literature. For the 4H-SiC detectors, a linewidth of 28keV FWHM was achieved, corresponding to an energy resolution of 0.5%.
Waid, Simon; Gsponer, Andreas; Renner, Elisabeth; Schmitzer, Claus; Kühteubl, Florian; Becker, Clara; Burin, Jürgen; Gaggl, Philipp; Prokopovich, Dale; Bergauer, Thomas
Pulsed RF knock-out extraction: a potential enabler for FLASH hadrontherapy in the Bragg peak Journal Article Open Access
In: Physics in Medicine & Biology, vol. 69, no. 12, pp. 125007, 2024.
@article{Waid_2024,
title = {Pulsed RF knock-out extraction: a potential enabler for FLASH hadrontherapy in the Bragg peak},
author = {Simon Waid and Andreas Gsponer and Elisabeth Renner and Claus Schmitzer and Florian Kühteubl and Clara Becker and Jürgen Burin and Philipp Gaggl and Dale Prokopovich and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2025/06/Waid_2024_Phys._Med._Biol._69_125007.pdf
https://arxiv.org/abs/2311.08960},
doi = {10.1088/1361-6560/ad5072},
year = {2024},
date = {2024-06-01},
urldate = {2024-06-01},
journal = {Physics in Medicine & Biology},
volume = {69},
number = {12},
pages = {125007},
publisher = {IOP Publishing},
abstract = {One challenge on the path to delivering FLASH-compatible beams with a synchrotron is facilitating an accurate dose control for the required ultra-high dose rates. We propose the use of pulsed RFKO extraction instead of continuous beam delivery as a way to control the dose delivered per Voxel. In a first feasibility test, dose rates in pulses of up to 600 Gy s−1 were observed, while the granularity at which the dose was delivered is expected to be well below 0.5 Gy.},
keywords = {OpenAccess},
pubstate = {published},
tppubtype = {article}
}
One challenge on the path to delivering FLASH-compatible beams with a synchrotron is facilitating an accurate dose control for the required ultra-high dose rates. We propose the use of pulsed RFKO extraction instead of continuous beam delivery as a way to control the dose delivered per Voxel. In a first feasibility test, dose rates in pulses of up to 600 Gy s−1 were observed, while the granularity at which the dose was delivered is expected to be well below 0.5 Gy.
Burin, Jürgen; Hahn, Christopher; Gaggl, Philipp; Gsponer, Andreas; Waid, Simon; Bergauer, Thomas
TCAD Simulations of Radiation Damage in 4H-SiC Proceedings Article
In: 2024 Austrochip Workshop on Microelectronics (Austrochip), pp. 1-4, 2024.
BibTeX |
@inproceedings{10716221,
title = {TCAD Simulations of Radiation Damage in 4H-SiC},
author = {Jürgen Burin and Christopher Hahn and Philipp Gaggl and Andreas Gsponer and Simon Waid and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2025/05/2407.16710v1.pdf
https://arxiv.org/abs/2407.16710},
doi = {10.1109/Austrochip62761.2024.10716221},
year = {2024},
date = {2024-01-01},
urldate = {2024-01-01},
booktitle = {2024 Austrochip Workshop on Microelectronics (Austrochip)},
pages = {1-4},
keywords = {Design automation;Silicon carbide;Current measurement;Radiation detectors;Particle measurements;Silicon;Microelectronics;P-i-n diodes;Electric fields;Current;TCAD simulations;4H silicon carbide (SiC);particle detector;radiation damage},
pubstate = {published},
tppubtype = {inproceedings}
}
Onder, Sebastian; Burin, Jürgen; Gaggl, Philipp; Gsponer, Andreas; Bergauer, Thomas; Waid, Simon
Towards Silicon Carbide Monolithic Active Pixel Radiation Sensors Proceedings Article
In: 2024 Austrochip Workshop on Microelectronics (Austrochip), pp. 1-4, 2024.
BibTeX |
@inproceedings{10716230,
title = {Towards Silicon Carbide Monolithic Active Pixel Radiation Sensors},
author = {Sebastian Onder and Jürgen Burin and Philipp Gaggl and Andreas Gsponer and Thomas Bergauer and Simon Waid},
url = {http://burin.at/wp-content/uploads/2025/05/OBGGBW24_AC.pdf},
doi = {10.1109/Austrochip62761.2024.10716230},
year = {2024},
date = {2024-01-01},
urldate = {2024-01-01},
booktitle = {2024 Austrochip Workshop on Microelectronics (Austrochip)},
pages = {1-4},
keywords = {Silicon carbide;Photonic band gap;Noise;Data acquisition;Detectors;Silicon;Spatial databases;Microelectronics;Transistors;Spatial resolution;high energy;detector;sensor;silicon carbide;asic;cmos;radiation hardness;ionizing radiation;maps;dmaps},
pubstate = {published},
tppubtype = {inproceedings}
}
Waid, Simon; Maier, Jürgen; Gaggl, Philipp; Gsponer, Andreas; Sieberer, Patrick; Babeluk, Maximilian; Bergauer, Thomas
Detector Development for Particle Physics Journal Article Open Access
In: Elektrotech. Inftech., vol. 141, pp. 20-28, 2023.
@article{WMGGSBB23:AC,
title = {Detector Development for Particle Physics},
author = {Simon Waid and Jürgen Maier and Philipp Gaggl and Andreas Gsponer and Patrick Sieberer and Maximilian Babeluk and Thomas Bergauer},
url = {http://burin.at/wp-content/uploads/2024/04/WMGGSBB24_EI.pdf
},
doi = {10.1007/s00502-023-01201-w},
year = {2023},
date = {2023-01-01},
urldate = {2023-01-01},
booktitle = {2023 Austrochip Workshop on Microelectronics (Austrochip)},
journal = { Elektrotech. Inftech.},
volume = {141},
pages = {20-28},
abstract = {In high-energy physics experiments, tracking and vertexing is nowadays mostly done using semiconductor detectors. Among the employed detectors are hybrid pixel sensors, passive sensors and recently also depleted monolithic active pixel sensors (DMAPS), which integrate the particle sensor with front-end electronics. Currently, the dominant material for the production of such sensors is silicon. However, the use of silicon carbide is currently being investigated. In this work we report on our progress on the development of silicon-based DMAPS. Further, we present two approaches for reading out passive silicon carbide detectors at particle rates from the kHz to the GHz range.},
keywords = {OpenAccess},
pubstate = {published},
tppubtype = {article}
}
In high-energy physics experiments, tracking and vertexing is nowadays mostly done using semiconductor detectors. Among the employed detectors are hybrid pixel sensors, passive sensors and recently also depleted monolithic active pixel sensors (DMAPS), which integrate the particle sensor with front-end electronics. Currently, the dominant material for the production of such sensors is silicon. However, the use of silicon carbide is currently being investigated. In this work we report on our progress on the development of silicon-based DMAPS. Further, we present two approaches for reading out passive silicon carbide detectors at particle rates from the kHz to the GHz range.
Maier, Jürgen; Steininger, Andreas; Najvirt, Robert
The Hidden Behavior of a D-Latch Journal Article Open Access
In: IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 4, pp. 1660-1670, 2023.
@article{MSN23:TCASI,
title = {The Hidden Behavior of a D-Latch},
author = {Jürgen Maier and Andreas Steininger and Robert Najvirt},
url = {http://burin.at/wp-content/uploads/2024/03/MSN23_TCASI.pdf},
doi = {10.1109/TCSI.2023.3237283},
year = {2023},
date = {2023-01-01},
urldate = {2023-01-01},
journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
volume = {70},
number = {4},
pages = {1660-1670},
abstract = {For clock and data transitions in close temporal proximity, synchronous memory elements potentially enter metastability, which leads to unintended output behavior. Although respective analyses in literature have already derived suitable explanations, almost all of them modeled the control (clock) signal transition with negligible rise/fall time. In modern circuits this assumption is, however, not reasonable any more. In fact, due to a finite slope, intermediate clock signal values have to be considered during a large share of the storage process, while their concrete impact is not yet sufficiently explored. In this paper we thus use static and dynamic considerations to thoroughly investigate the behavior of a latch for arbitrary analog control, data and output values, i.e., during the storage process. Basic circuit considerations allow us to derive a unified model which identifies the latch as a Schmitt Trigger with vastly varying hysteresis. We verify the correctness of our predictions by comparison to analog SPICE simulations. Finally we are able to generalize our findings and thus provide explanations for yet unexplained behavior reported in literature.},
key = {2023},
keywords = {featured, OpenAccess},
pubstate = {published},
tppubtype = {article}
}
For clock and data transitions in close temporal proximity, synchronous memory elements potentially enter metastability, which leads to unintended output behavior. Although respective analyses in literature have already derived suitable explanations, almost all of them modeled the control (clock) signal transition with negligible rise/fall time. In modern circuits this assumption is, however, not reasonable any more. In fact, due to a finite slope, intermediate clock signal values have to be considered during a large share of the storage process, while their concrete impact is not yet sufficiently explored. In this paper we thus use static and dynamic considerations to thoroughly investigate the behavior of a latch for arbitrary analog control, data and output values, i.e., during the storage process. Basic circuit considerations allow us to derive a unified model which identifies the latch as a Schmitt Trigger with vastly varying hysteresis. We verify the correctness of our predictions by comparison to analog SPICE simulations. Finally we are able to generalize our findings and thus provide explanations for yet unexplained behavior reported in literature.
Gsponer, Andreas; Gaggl, Philipp; Burin, Jürgen; Thalmeier, Richard; Waid, Simon; Bergauer, Thomas
Neutron radiation induced effects in 4H-SiC PiN diodes Journal Article Open Access
In: Journal of Instrumentation, vol. 18, no. 11, pp. C11027, 2023.
@article{GGBTWB23:JoI,
title = {Neutron radiation induced effects in 4H-SiC PiN diodes},
author = {Andreas Gsponer and Philipp Gaggl and Jürgen Burin and Richard Thalmeier and Simon Waid and Thomas Bergauer},
url = {https://arxiv.org/abs/2310.02047},
doi = {10.1088/1748-0221/18/11/C11027},
year = {2023},
date = {2023-11-01},
urldate = {2023-11-01},
journal = {Journal of Instrumentation},
volume = {18},
number = {11},
pages = {C11027},
publisher = {IOP Publishing},
abstract = {Silicon carbide (SiC) is a wide band gap semiconductor and an attractive candidate for applications in harsh environments such as space, fusion, or future high luminosity colliders. Due to the large band gap, the leakage currents in SiC devices are extremely small, even after irradiation to very high fluences, enabling operation without cooling and at high temperatures. This study investigates the effect of neutron irradiation on 50 μm p-n 4H-SiC diodes using current-voltage, capacitance-voltage, and charge collection efficiency (CCE) measurements up to neutron fluences of 1 × 1016neq/cm2. The leakage currents of the investigated devices remained extremely small, below 10 pA at 1.1 kV reverse bias. In the forward bias, a remarkable drop of the current was observed, which was attributed to an increased epi resistivity due to compensation of the epi layer doping by deep-level defects. The CCE was evaluated for alpha particles from a radioactive source, a 62.4 MeV proton beam at the MedAustron ion therapy center and using UV-TCT. The charge collection efficiency in reverse bias was shown to scale directly with the 1 MeV equivalent fluence Φeq as CCE∝Φeq-0.63±0.01. A CCE better than 50% was able to be obtained for fluences up to 1 × 1015neq/cm2. Because of the low currents in the forward direction, particle detection was also possible in forward bias, where the CCE was found to be increased relative to reverse bias. Furthermore, a significant dependency on the amount of injected charge was observed, with the CCE surpassing 100% in alpha and UV-TCT measurements, requiring further systematic investigation.},
keywords = {OpenAccess},
pubstate = {published},
tppubtype = {article}
}
Silicon carbide (SiC) is a wide band gap semiconductor and an attractive candidate for applications in harsh environments such as space, fusion, or future high luminosity colliders. Due to the large band gap, the leakage currents in SiC devices are extremely small, even after irradiation to very high fluences, enabling operation without cooling and at high temperatures. This study investigates the effect of neutron irradiation on 50 μm p-n 4H-SiC diodes using current-voltage, capacitance-voltage, and charge collection efficiency (CCE) measurements up to neutron fluences of 1 × 1016neq/cm2. The leakage currents of the investigated devices remained extremely small, below 10 pA at 1.1 kV reverse bias. In the forward bias, a remarkable drop of the current was observed, which was attributed to an increased epi resistivity due to compensation of the epi layer doping by deep-level defects. The CCE was evaluated for alpha particles from a radioactive source, a 62.4 MeV proton beam at the MedAustron ion therapy center and using UV-TCT. The charge collection efficiency in reverse bias was shown to scale directly with the 1 MeV equivalent fluence Φeq as CCE∝Φeq-0.63±0.01. A CCE better than 50% was able to be obtained for fluences up to 1 × 1015neq/cm2. Because of the low currents in the forward direction, particle detection was also possible in forward bias, where the CCE was found to be increased relative to reverse bias. Furthermore, a significant dependency on the amount of injected charge was observed, with the CCE surpassing 100% in alpha and UV-TCT measurements, requiring further systematic investigation.
Ferdowsi, Arman; Maier, Jürgen; Öhlinger, Daniel; Schmid, Ulrich
A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate Proceedings Article
In: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1461-1466, 2022.
@inproceedings{FMOS22:DATE,
title = {A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate},
author = {Arman Ferdowsi and Jürgen Maier and Daniel Öhlinger and Ulrich Schmid},
url = {http://burin.at/wp-content/uploads/2024/03/FMOS22_DATE.pdf
https://arxiv.org/abs/2111.11182},
doi = {10.23919/DATE54114.2022.9774547},
year = {2022},
date = {2022-01-01},
urldate = {2022-01-01},
booktitle = {2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
pages = {1461-1466},
abstract = {Faithfully representing small delay variations caused by transitions on different inputs in close temporal proximity is a challenging task for digital circuit delay models. In this paper, we show that a simple hybrid model, derived from considering transistors as ideal switches in a simple RC model, leads to a surprisingly accurate model. By analytically solving the resulting ODEs for a NOR gate, explicit expressions for the delay are derived. In addition, we experimentally compare our model's predictions to SPICE simulations and to existing delay models.},
key = {2022},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Faithfully representing small delay variations caused by transitions on different inputs in close temporal proximity is a challenging task for digital circuit delay models. In this paper, we show that a simple hybrid model, derived from considering transistors as ideal switches in a simple RC model, leads to a surprisingly accurate model. By analytically solving the resulting ODEs for a NOR gate, explicit expressions for the delay are derived. In addition, we experimentally compare our model's predictions to SPICE simulations and to existing delay models.
Maier, Jürgen
Proper Abstractions for Digital Electronic Circuits: A Physically Guided Approach PhD Thesis Open Access
TU Wien, Vienna, Austria, 2022.
@phdthesis{M22:PHD,
title = {Proper Abstractions for Digital Electronic Circuits: A Physically Guided Approach},
author = {Jürgen Maier},
url = {http://burin.at/wp-content/uploads/2024/03/Diss_Maier_Juergen.pdf},
doi = {10.34726/hss.2022.102506},
year = {2022},
date = {2022-01-01},
urldate = {2022-01-01},
school = {TU Wien, Vienna, Austria},
abstract = {Over the last decades, major improvements in handling semiconductor materials led
to a massive shrinkage of transistor sizes that, in turn, enabled engineers to realize
larger and faster digital circuits. The resulting increase in complexity had, however,
negative effects on verification: Although nowadays highly accurate models of the main
physical processes, which govern the behavior of a circuit, are available, the size and
complexity of these models makes it impossible to finish simulations/computations in
reasonable time. One possible solution is to introduce abstractions, which have the
goal to reduce the verification effort by hiding certain details while preserving accuracy.
Naturally, developing proper abstractions is a very challenging task: Too little or the
wrong information provide an incomplete picture while excessive models tend to be slow.
In this thesis, we, thus, study proper abstractions for digital electronic circuits. In
our opinion, the best results are achieved by (i) understanding the underlying physical
behaviors and (ii) picking appropriate abstract models and parameters based on the
gained insights. This effectively reduces the task to observation and conclusion, so no
assumptions or even guessing is required. Whereas the abstractions and models presented
in this thesis are not meant to replace existing approaches, they provide an alternative
in between highly sophisticated methods (e.g., ordinary differential equations in analog
simulations) and overly simplified ones (e.g., digital models utilizing pure and inertial
delays). Overall, we aim at achieving reliable models, which provide high coverage and
accuracy at low verification efforts compared to existing approaches.
To achieve this goal, we thoroughly studied the following model domains:
1) Analog abstractions: To describe the analog behavior of various logic gates in a
simplified fashion, we develop new models based on physically inspired basic transistor
equations. Although these provide reasonably accurate results, the required effort is
still too high for large-scale verification. Consequently, we employ further abstractions.
Using analytic calculations and fittings, we aim at mathematical functions that allow an
approximation of the analog waveforms. We show that unique rising and falling full-range
switching waveforms provide a very good basis, since their proper combination (more
specifically, the addition of time-shifted versions) is able to closely approximate every
observed shape. We are convinced that our approach will enable the development of an
analog simulation suite with high accuracy, which only needs a fraction of the verification
time required for established analog simulation methods.
2) Digital abstractions: We thoroughly analyze and extend the Involution Delay
Model, the only candidate for a faithful delay estimation method known so far. Based
on physically guided considerations, we (i) identify several shortcomings, (ii) provide a
proper explanation and (iii) develop improvements that remove the observed problems.
More specifically, we show how to calculate delay functions analytically, relax certain
restrictions that impaired easy applicability, and even introduce non-determinism to
improve the model coverage. Formal proofs and deductions are used to show the
correctness of our new abstractions. Simulations of simple circuits allow, for the first
time, a quantitative evaluation of the superior accuracy and the not insignificant, but
quite reasonable, overhead. This enables a fair comparison of the Involution Delay Model
and state-of-the-art digital delay models.
3) We complement our efforts on analog and digital abstractions by an in-depth
investigation of the Schmitt Trigger, in particular, its susceptibility to metastability
(intermediary output values, late transitions). By introducing and using various novel
methods, we are able to characterize the metastable behavior of this gate, i.e., when to
expect which effects. Exploiting this knowledge, we show, based on analog simulations,
how to generate an arbitrary output waveform in a common implementation by controlling
the input accordingly. We also argue that cascading Schmitt Triggers, as it is done with
Flip-Flops in a synchronizer, only improves the situation partially, as new undesired
effects are added. Overall, our results, however, show that a very fine-grained control of
the input is demanded to exploit metastable behavior in the Schmitt Trigger, making it
very unlikely in normal operation.
From the answers we obtained by investigating these interesting research questions,
we can conclude that there is no “silver bullet” w.r.t. modeling abstractions. Every
approach is unique in some respect and thus requires a careful analysis of the governing
physical behavior to achieve the optimal performance, accuracy and coverage.},
key = {2022},
keywords = {featured, OpenAccess},
pubstate = {published},
tppubtype = {phdthesis}
}
Over the last decades, major improvements in handling semiconductor materials led
to a massive shrinkage of transistor sizes that, in turn, enabled engineers to realize
larger and faster digital circuits. The resulting increase in complexity had, however,
negative effects on verification: Although nowadays highly accurate models of the main
physical processes, which govern the behavior of a circuit, are available, the size and
complexity of these models makes it impossible to finish simulations/computations in
reasonable time. One possible solution is to introduce abstractions, which have the
goal to reduce the verification effort by hiding certain details while preserving accuracy.
Naturally, developing proper abstractions is a very challenging task: Too little or the
wrong information provide an incomplete picture while excessive models tend to be slow.
In this thesis, we, thus, study proper abstractions for digital electronic circuits. In
our opinion, the best results are achieved by (i) understanding the underlying physical
behaviors and (ii) picking appropriate abstract models and parameters based on the
gained insights. This effectively reduces the task to observation and conclusion, so no
assumptions or even guessing is required. Whereas the abstractions and models presented
in this thesis are not meant to replace existing approaches, they provide an alternative
in between highly sophisticated methods (e.g., ordinary differential equations in analog
simulations) and overly simplified ones (e.g., digital models utilizing pure and inertial
delays). Overall, we aim at achieving reliable models, which provide high coverage and
accuracy at low verification efforts compared to existing approaches.
To achieve this goal, we thoroughly studied the following model domains:
1) Analog abstractions: To describe the analog behavior of various logic gates in a
simplified fashion, we develop new models based on physically inspired basic transistor
equations. Although these provide reasonably accurate results, the required effort is
still too high for large-scale verification. Consequently, we employ further abstractions.
Using analytic calculations and fittings, we aim at mathematical functions that allow an
approximation of the analog waveforms. We show that unique rising and falling full-range
switching waveforms provide a very good basis, since their proper combination (more
specifically, the addition of time-shifted versions) is able to closely approximate every
observed shape. We are convinced that our approach will enable the development of an
analog simulation suite with high accuracy, which only needs a fraction of the verification
time required for established analog simulation methods.
2) Digital abstractions: We thoroughly analyze and extend the Involution Delay
Model, the only candidate for a faithful delay estimation method known so far. Based
on physically guided considerations, we (i) identify several shortcomings, (ii) provide a
proper explanation and (iii) develop improvements that remove the observed problems.
More specifically, we show how to calculate delay functions analytically, relax certain
restrictions that impaired easy applicability, and even introduce non-determinism to
improve the model coverage. Formal proofs and deductions are used to show the
correctness of our new abstractions. Simulations of simple circuits allow, for the first
time, a quantitative evaluation of the superior accuracy and the not insignificant, but
quite reasonable, overhead. This enables a fair comparison of the Involution Delay Model
and state-of-the-art digital delay models.
3) We complement our efforts on analog and digital abstractions by an in-depth
investigation of the Schmitt Trigger, in particular, its susceptibility to metastability
(intermediary output values, late transitions). By introducing and using various novel
methods, we are able to characterize the metastable behavior of this gate, i.e., when to
expect which effects. Exploiting this knowledge, we show, based on analog simulations,
how to generate an arbitrary output waveform in a common implementation by controlling
the input accordingly. We also argue that cascading Schmitt Triggers, as it is done with
Flip-Flops in a synchronizer, only improves the situation partially, as new undesired
effects are added. Overall, our results, however, show that a very fine-grained control of
the input is demanded to exploit metastable behavior in the Schmitt Trigger, making it
very unlikely in normal operation.
From the answers we obtained by investigating these interesting research questions,
we can conclude that there is no “silver bullet” w.r.t. modeling abstractions. Every
approach is unique in some respect and thus requires a careful analysis of the governing
physical behavior to achieve the optimal performance, accuracy and coverage.
to a massive shrinkage of transistor sizes that, in turn, enabled engineers to realize
larger and faster digital circuits. The resulting increase in complexity had, however,
negative effects on verification: Although nowadays highly accurate models of the main
physical processes, which govern the behavior of a circuit, are available, the size and
complexity of these models makes it impossible to finish simulations/computations in
reasonable time. One possible solution is to introduce abstractions, which have the
goal to reduce the verification effort by hiding certain details while preserving accuracy.
Naturally, developing proper abstractions is a very challenging task: Too little or the
wrong information provide an incomplete picture while excessive models tend to be slow.
In this thesis, we, thus, study proper abstractions for digital electronic circuits. In
our opinion, the best results are achieved by (i) understanding the underlying physical
behaviors and (ii) picking appropriate abstract models and parameters based on the
gained insights. This effectively reduces the task to observation and conclusion, so no
assumptions or even guessing is required. Whereas the abstractions and models presented
in this thesis are not meant to replace existing approaches, they provide an alternative
in between highly sophisticated methods (e.g., ordinary differential equations in analog
simulations) and overly simplified ones (e.g., digital models utilizing pure and inertial
delays). Overall, we aim at achieving reliable models, which provide high coverage and
accuracy at low verification efforts compared to existing approaches.
To achieve this goal, we thoroughly studied the following model domains:
1) Analog abstractions: To describe the analog behavior of various logic gates in a
simplified fashion, we develop new models based on physically inspired basic transistor
equations. Although these provide reasonably accurate results, the required effort is
still too high for large-scale verification. Consequently, we employ further abstractions.
Using analytic calculations and fittings, we aim at mathematical functions that allow an
approximation of the analog waveforms. We show that unique rising and falling full-range
switching waveforms provide a very good basis, since their proper combination (more
specifically, the addition of time-shifted versions) is able to closely approximate every
observed shape. We are convinced that our approach will enable the development of an
analog simulation suite with high accuracy, which only needs a fraction of the verification
time required for established analog simulation methods.
2) Digital abstractions: We thoroughly analyze and extend the Involution Delay
Model, the only candidate for a faithful delay estimation method known so far. Based
on physically guided considerations, we (i) identify several shortcomings, (ii) provide a
proper explanation and (iii) develop improvements that remove the observed problems.
More specifically, we show how to calculate delay functions analytically, relax certain
restrictions that impaired easy applicability, and even introduce non-determinism to
improve the model coverage. Formal proofs and deductions are used to show the
correctness of our new abstractions. Simulations of simple circuits allow, for the first
time, a quantitative evaluation of the superior accuracy and the not insignificant, but
quite reasonable, overhead. This enables a fair comparison of the Involution Delay Model
and state-of-the-art digital delay models.
3) We complement our efforts on analog and digital abstractions by an in-depth
investigation of the Schmitt Trigger, in particular, its susceptibility to metastability
(intermediary output values, late transitions). By introducing and using various novel
methods, we are able to characterize the metastable behavior of this gate, i.e., when to
expect which effects. Exploiting this knowledge, we show, based on analog simulations,
how to generate an arbitrary output waveform in a common implementation by controlling
the input accordingly. We also argue that cascading Schmitt Triggers, as it is done with
Flip-Flops in a synchronizer, only improves the situation partially, as new undesired
effects are added. Overall, our results, however, show that a very fine-grained control of
the input is demanded to exploit metastable behavior in the Schmitt Trigger, making it
very unlikely in normal operation.
From the answers we obtained by investigating these interesting research questions,
we can conclude that there is no “silver bullet” w.r.t. modeling abstractions. Every
approach is unique in some respect and thus requires a careful analysis of the governing
physical behavior to achieve the optimal performance, accuracy and coverage.
Maier, Jürgen; Hartl-Nesic, Christian; Steininger, Andreas
Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses Journal Article Open Access
In: IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 3, pp. 1013-1026, 2022.
@article{9646276b,
title = {Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses},
author = {Jürgen Maier and Christian Hartl-Nesic and Andreas Steininger},
url = {http://burin.at/wp-content/uploads/2024/03/MHS21_TCASI.pdf},
doi = {10.1109/TCSI.2021.3130349},
year = {2022},
date = {2022-01-01},
urldate = {2022-01-01},
journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
volume = {69},
number = {3},
pages = {1013-1026},
abstract = {Schmitt-Triggers (S/Ts) are often utilized to clean noisy analog signals at intermediate voltage values in digital circuits. However, they are vulnerable to metastability, which may cause the same undesired non-digital output behavior that was supposed to be removed in the first place. To enable an efficient characterization of static and dynamic metastability properties of S/Ts (e.g., the metastable voltages, the resolution time constants and the overall total resolution times), this work introduces multiple simulation approaches based on control theory, AC, DC and transient analyses. The accuracy and runtime of all methods are compared and discussed by applying them to an analytically describable idealized circuit model as well as three common circuit implementations. Altogether, this work represents a comprehensive resource for investigating the metastable behavior in S/Ts. Even more, the proposed methods are applicable beyond the S/T, enabling an efficient characterization of static and dynamic metastable behavior in general circuits as well.},
keywords = {OpenAccess, Voltage;Integrated circuit modeling;Trajectory;Analytical models;Latches;Digital circuits;Voltage measurement;Schmitt-trigger;metastability characterization;instability analysis;metastable states},
pubstate = {published},
tppubtype = {article}
}
Schmitt-Triggers (S/Ts) are often utilized to clean noisy analog signals at intermediate voltage values in digital circuits. However, they are vulnerable to metastability, which may cause the same undesired non-digital output behavior that was supposed to be removed in the first place. To enable an efficient characterization of static and dynamic metastability properties of S/Ts (e.g., the metastable voltages, the resolution time constants and the overall total resolution times), this work introduces multiple simulation approaches based on control theory, AC, DC and transient analyses. The accuracy and runtime of all methods are compared and discussed by applying them to an analytically describable idealized circuit model as well as three common circuit implementations. Altogether, this work represents a comprehensive resource for investigating the metastable behavior in S/Ts. Even more, the proposed methods are applicable beyond the S/T, enabling an efficient characterization of static and dynamic metastable behavior in general circuits as well.
Öhlinger, Daniel; Maier, Jürgen; Függer, Matthias; Schmid, Ulrich
The Involution Tool for Accurate Digital Timing and Power Analysis Journal Article Open Access
In: Integration, vol. 76, pp. 87-98, 2021, ISSN: 0167-9260.
@article{OHLINGER202187,
title = {The Involution Tool for Accurate Digital Timing and Power Analysis},
author = {Daniel Öhlinger and Jürgen Maier and Matthias Függer and Ulrich Schmid},
url = {http://burin.at/wp-content/uploads/2024/03/OMFS20_INTEGRATION.pdf},
doi = {https://doi.org/10.1016/j.vlsi.2020.09.007},
issn = {0167-9260},
year = {2021},
date = {2021-01-01},
urldate = {2021-01-01},
journal = {Integration},
volume = {76},
pages = {87-98},
abstract = {We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuits that supports the involution delay model (Függer et al. 2019). Unlike the pure and inertial delay models typically used in digital timing analysis tools, the involution model faithfully captures short pulse propagation and related effects. Our Involution Tool facilitates experimental accuracy evaluation of variants of involution models, by comparing their timing and power predictions to those from SPICE and standard timing analysis tools. The tool is easily customizable w.r.t. instances of the involution model and circuits, and supports automatic test case generation and parameter sweeping. We demonstrate the capabilities of the Involution Tool by providing timing and power analysis results for three different circuits, namely, an inverter tree, the clock tree of an open-source processor, and a combinational circuit that involves multi-input NAND gates. Our evaluation uses two different technologies (15 nm and 65 nm CMOS), and three different variants of involution channels (Exp, Hill and SumExp-channels). It turns out that the timing and power predictions of all involution models are significantly better than the predictions obtained by standard digital simulations for the inverter tree and the clock tree, with the SumExp-channel channel clearly outperforming the others. For the NAND circuit, the performance of any involution model is generally comparable but not significantly better than that of standard models, however, which reveals some shortcomings of the existing involution channels for modeling multi-input gates.},
keywords = {Delay models, Design tools, Digital timing simulation, Glitch propagation, OpenAccess, Pulse degradation},
pubstate = {published},
tppubtype = {article}
}
We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuits that supports the involution delay model (Függer et al. 2019). Unlike the pure and inertial delay models typically used in digital timing analysis tools, the involution model faithfully captures short pulse propagation and related effects. Our Involution Tool facilitates experimental accuracy evaluation of variants of involution models, by comparing their timing and power predictions to those from SPICE and standard timing analysis tools. The tool is easily customizable w.r.t. instances of the involution model and circuits, and supports automatic test case generation and parameter sweeping. We demonstrate the capabilities of the Involution Tool by providing timing and power analysis results for three different circuits, namely, an inverter tree, the clock tree of an open-source processor, and a combinational circuit that involves multi-input NAND gates. Our evaluation uses two different technologies (15 nm and 65 nm CMOS), and three different variants of involution channels (Exp, Hill and SumExp-channels). It turns out that the timing and power predictions of all involution models are significantly better than the predictions obtained by standard digital simulations for the inverter tree and the clock tree, with the SumExp-channel channel clearly outperforming the others. For the NAND circuit, the performance of any involution model is generally comparable but not significantly better than that of standard models, however, which reveals some shortcomings of the existing involution channels for modeling multi-input gates.
Maier, J.; Öhlinger, D.; Schmid, U.; Függer, M.; Nowak, T.
A Composable Glitch-Aware Delay Model Proceedings Article Open Access
In: Proceedings of the 2021 on Great Lakes Symposium on VLSI, pp. 147–154, Association for Computing Machinery, Virtual Event, USA, 2021, ISBN: 9781450383936.
@inproceedings{MOSFN21:GLSVLSI,
title = {A Composable Glitch-Aware Delay Model},
author = {J. Maier and D. Öhlinger and U. Schmid and M. Függer and T. Nowak},
url = {http://burin.at/wp-content/uploads/2024/03/MOSFN21_GLSVLSI.pdf},
doi = {10.1145/3453688.3461519},
isbn = {9781450383936},
year = {2021},
date = {2021-01-01},
urldate = {2021-01-01},
booktitle = {Proceedings of the 2021 on Great Lakes Symposium on VLSI},
pages = {147–154},
publisher = {Association for Computing Machinery},
address = {Virtual Event, USA},
series = {GLSVLSI '21},
abstract = {We introduce the Composable Involution Delay Model (CIDM) for fast
and accurate digital simulation. It is based on the Involution
Delay Model (IDM) [Függer et al., IEEE TCAD 2020], which
has been shown to be the only existing candidate model for
faithful glitch propagation. The IDM, however, has
shortcomings that limit its applicability. Our CIDM thus
reduces the characterization effort by allowing independent
discretization thresholds, improves composability and
increases the modeling power by exposing canceled pulse trains
at the gate interconnect. We formally show that, despite these
improvements, the CIDM still retains the IDM's faithfulness.},
key = {2021},
keywords = {composable delay estimation model, Digital timing simulation, faithful glitch propagation, OpenAccess, Pulse degradation},
pubstate = {published},
tppubtype = {inproceedings}
}
We introduce the Composable Involution Delay Model (CIDM) for fast
and accurate digital simulation. It is based on the Involution
Delay Model (IDM) [Függer et al., IEEE TCAD 2020], which
has been shown to be the only existing candidate model for
faithful glitch propagation. The IDM, however, has
shortcomings that limit its applicability. Our CIDM thus
reduces the characterization effort by allowing independent
discretization thresholds, improves composability and
increases the modeling power by exposing canceled pulse trains
at the gate interconnect. We formally show that, despite these
improvements, the CIDM still retains the IDM's faithfulness.
and accurate digital simulation. It is based on the Involution
Delay Model (IDM) [Függer et al., IEEE TCAD 2020], which
has been shown to be the only existing candidate model for
faithful glitch propagation. The IDM, however, has
shortcomings that limit its applicability. Our CIDM thus
reduces the characterization effort by allowing independent
discretization thresholds, improves composability and
increases the modeling power by exposing canceled pulse trains
at the gate interconnect. We formally show that, despite these
improvements, the CIDM still retains the IDM's faithfulness.
Maier, Jürgen
Gain and Pain of a Reliable Delay Model Proceedings Article
In: 2021 24th Euromicro Conference on Digital System Design (DSD), pp. 246-250, 2021.
@inproceedings{M21:DSD,
title = {Gain and Pain of a Reliable Delay Model},
author = {Jürgen Maier},
url = {http://burin.at/wp-content/uploads/2024/03/M21_DSD.pdf
https://www.techrxiv.org/articles/preprint/Gain_and_Pain_of_a_Reliable_Delay_Model/14872116
https://arxiv.org/abs/2107.06814},
doi = {10.1109/DSD53832.2021.00046},
year = {2021},
date = {2021-01-01},
urldate = {2021-01-01},
booktitle = {2021 24th Euromicro Conference on Digital System Design (DSD)},
pages = {246-250},
abstract = {In this paper we evaluate a promising delay estimation method, the Involution Delay Model. We apply it to three simple circuits (a combinatorial loop, an SR latch and an adder), interpret the delivered results and determine realistic overhead estimations. Comparisons to analog SPICE simulations reveal fine-grained behavioral coverage, whereat the commonly used digital inertial delay model shows severe shortcomings. Overall, the Involution Delay Model is able to identify a wide range of malicious behavior and is thus a viable upgrade to available delay models in modern digital timing simulation tools.},
key = {2021},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
In this paper we evaluate a promising delay estimation method, the Involution Delay Model. We apply it to three simple circuits (a combinatorial loop, an SR latch and an adder), interpret the delivered results and determine realistic overhead estimations. Comparisons to analog SPICE simulations reveal fine-grained behavioral coverage, whereat the commonly used digital inertial delay model shows severe shortcomings. Overall, the Involution Delay Model is able to identify a wide range of malicious behavior and is thus a viable upgrade to available delay models in modern digital timing simulation tools.
Öhlinger, D.; Maier, J.; Függer, M.; Schmid, U.
The Involution Tool for Accurate Digital Timing and Power Analysis Proceedings Article
In: 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 1-8, 2019.
@inproceedings{OMFS19:PATMOS,
title = {The Involution Tool for Accurate Digital Timing and Power Analysis},
author = {D. Öhlinger and J. Maier and M. Függer and U. Schmid},
url = {http://burin.at/wp-content/uploads/2024/03/OMFS19_PATMOS.pdf},
doi = {10.1109/PATMOS.2019.8862165},
year = {2019},
date = {2019-07-01},
urldate = {2019-07-01},
booktitle = {2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
pages = {1-8},
abstract = {We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuit (Involution Tool) which employs the involution delay model introduced by Fugger et al. at DATE'15. Unlike the pure and inertial delaÿ models typically used in digital timing analysis tools, the involution model faithfully captures pulse propagation. The presented tool is able to quantify for the first time the accuracy of the latter by facilitating comparisons of its timing and power predictions with both SPICE-generated results and results achieved by standard timing analysis tools. It is easily customizable, both w.r.t. different instances of the involution model and different circuits, and supports automatic test case generation, including parameter sweeping. We demonstrate its capabilities by providing timing and power analysis results for three circuits in varying technologies: an inverter tree, the clock tree of an open-source processor, and a combinational circuit that involves multi-input NAND gates. It turns out that the timing and power predictions of two natural types of involution models are significantly better than the predictions obtained by standard digital simulations for the inverter tree and the clock tree. For the NAND circuit, the performance is comparable but not significantly better. Our simulations thus confirm the benefits of the involution model, but also demonstrate shortcomings for multi-input gates.},
key = {2019},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuit (Involution Tool) which employs the involution delay model introduced by Fugger et al. at DATE'15. Unlike the pure and inertial delaÿ models typically used in digital timing analysis tools, the involution model faithfully captures pulse propagation. The presented tool is able to quantify for the first time the accuracy of the latter by facilitating comparisons of its timing and power predictions with both SPICE-generated results and results achieved by standard timing analysis tools. It is easily customizable, both w.r.t. different instances of the involution model and different circuits, and supports automatic test case generation, including parameter sweeping. We demonstrate its capabilities by providing timing and power analysis results for three circuits in varying technologies: an inverter tree, the clock tree of an open-source processor, and a combinational circuit that involves multi-input NAND gates. It turns out that the timing and power predictions of two natural types of involution models are significantly better than the predictions obtained by standard digital simulations for the inverter tree and the clock tree. For the NAND circuit, the performance is comparable but not significantly better. Our simulations thus confirm the benefits of the involution model, but also demonstrate shortcomings for multi-input gates.
Paulweber, P.; Maier, J.; Cortadella, J.
Unified (A)Synchronous Circuit Development Proceedings Article Open Access
In: 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2019, (Fresh idea accepted for ASYNC'19).
@inproceedings{PMC19:ASYNC,
title = {Unified (A)Synchronous Circuit Development},
author = {P. Paulweber and J. Maier and J. Cortadella},
url = {http://burin.at/wp-content/uploads/2024/03/PMC19_ASYNC.pdf
http://hdl.handle.net/20.500.12708/484},
year = {2019},
date = {2019-05-01},
urldate = {2019-05-01},
booktitle = {2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)},
abstract = {Despite its development several decades ago and several very beneficial properties asynchronous logic design, which is data driven and runs as fast as possible in all situations, is rarely used nowadays. Reasons are of course its disadvantageous properties such as bad testability but also required sophisticated knowledge for designers and missing tools. In this paper we draw a path to tackle the latter points by suggesting a tool/way to generate multiple circuit implementations from a single description. We are aiming to convert specifications written in various input languages, e.g. C or VHDL, to an unified Internal Representation (IR). This IR is composed of building blocks (semantic vocabulary) specified through the Abstract State Machine (ASM) based formal method. The ASM artifact is then used to generate the circuit in the desired (a)synchronous design style. As short term goal we aim to train developers by reading synchronous descriptions and converting them to asynchronous designs however in the long run we hope to establish a unified path for circuit development, which only requires an abstract behavioral description.},
key = {2019},
note = {Fresh idea accepted for ASYNC'19},
keywords = {Abstract State Machines, Asynchronous Logic, OpenAccess},
pubstate = {published},
tppubtype = {inproceedings}
}
Despite its development several decades ago and several very beneficial properties asynchronous logic design, which is data driven and runs as fast as possible in all situations, is rarely used nowadays. Reasons are of course its disadvantageous properties such as bad testability but also required sophisticated knowledge for designers and missing tools. In this paper we draw a path to tackle the latter points by suggesting a tool/way to generate multiple circuit implementations from a single description. We are aiming to convert specifications written in various input languages, e.g. C or VHDL, to an unified Internal Representation (IR). This IR is composed of building blocks (semantic vocabulary) specified through the Abstract State Machine (ASM) based formal method. The ASM artifact is then used to generate the circuit in the desired (a)synchronous design style. As short term goal we aim to train developers by reading synchronous descriptions and converting them to asynchronous designs however in the long run we hope to establish a unified path for circuit development, which only requires an abstract behavioral description.
Maier, J.; Steininger, A.
Efficient Metastability Characterization for Schmitt-Triggers Proceedings Article
In: 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 124-133, 2019.
@inproceedings{MS19:ASYNC,
title = {Efficient Metastability Characterization for Schmitt-Triggers},
author = {J. Maier and A. Steininger},
url = {http://burin.at/wp-content/uploads/2024/03/MS19_ASYNC.pdf
https://arxiv.org/abs/2006.14001},
doi = {10.1109/ASYNC.2019.00024},
year = {2019},
date = {2019-05-01},
urldate = {2019-05-01},
booktitle = {2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)},
pages = {124-133},
abstract = {Despite their attractiveness as metastability filters, Schmitt-Triggers can suffer from metastability themselves. Therefore, in the selection or construction of a suitable Schmitt-Trigger implementation, it is a necessity to accurately determine the metastable behavior. Only then one is able to compare different designs and thus guide proper optimizations, and only then one can assess the potential for residual metastable upsets. However, while the state of the art provides a lot of research and practical characterization approaches for flip-flops, comparatively little is known about Schmitt-Trigger characterization. Unlike the flip-flop with its single metastable point, the Schmitt-Trigger exhibits a whole range of metastable points depending on the input voltage. Thus the task of characterization gets much more challenging. In this paper we present different approaches to determine the metastable behavior of Schmitt-Triggers using novel methods and mechanisms. We compare their accuracy and runtime by applying them to three common circuit implementations. The achieved results are then used to reason about the metastable behavior of the chosen designs which turns out to be problematic in some cases. Overall the approaches proposed in this paper are generic and can be extended beyond the Schmitt-Trigger, i.e., to efficiently characterize metastable states in other circuits as well.},
key = {2019},
keywords = {Metastability Characterization, SPICE},
pubstate = {published},
tppubtype = {inproceedings}
}
Despite their attractiveness as metastability filters, Schmitt-Triggers can suffer from metastability themselves. Therefore, in the selection or construction of a suitable Schmitt-Trigger implementation, it is a necessity to accurately determine the metastable behavior. Only then one is able to compare different designs and thus guide proper optimizations, and only then one can assess the potential for residual metastable upsets. However, while the state of the art provides a lot of research and practical characterization approaches for flip-flops, comparatively little is known about Schmitt-Trigger characterization. Unlike the flip-flop with its single metastable point, the Schmitt-Trigger exhibits a whole range of metastable points depending on the input voltage. Thus the task of characterization gets much more challenging. In this paper we present different approaches to determine the metastable behavior of Schmitt-Triggers using novel methods and mechanisms. We compare their accuracy and runtime by applying them to three common circuit implementations. The achieved results are then used to reason about the metastable behavior of the chosen designs which turns out to be problematic in some cases. Overall the approaches proposed in this paper are generic and can be extended beyond the Schmitt-Trigger, i.e., to efficiently characterize metastable states in other circuits as well.
Maier, J.; Függer, M.; Nowak, T.; Schmid, U.
Transistor-Level Analysis of Dynamic Delay Models Proceedings Article
In: 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 76-85, 2019.
@inproceedings{MFNS19:ASYNC,
title = {Transistor-Level Analysis of Dynamic Delay Models},
author = {J. Maier and M. Függer and T. Nowak and U. Schmid},
url = {http://burin.at/wp-content/uploads/2024/03/MFNS19_ASYNC.pdf},
doi = {10.1109/ASYNC.2019.00019},
year = {2019},
date = {2019-05-01},
urldate = {2019-05-01},
booktitle = {2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)},
pages = {76-85},
abstract = {Delay estimation is a crucial task in digital circuit design as it provides the possibility to assure the desired functionality, but also prevents undesired behavior very early. For this purpose elaborate delay models like the Degradation Delay Model (DDM) and the Involution Delay Model (IDM) have been proposed in the past, which facilitate accurate dynamic timing analysis: Both use delay functions that determine the delay of the current input transition based on the time difference T to the previous output one. Currently, however, extensive analog simulations are necessary to determine the (parameters of the) delay function, which is a very time-consuming and cumbersome task and thus limits the applicability of these models. In this paper, we therefore thoroughly investigate the characterization procedures of a CMOS inverter on the transistor level in order to derive analytical expressions for the delay functions. Based on reasonably simple transistor models we identify three operation regions, each described by a different estimation function. Using simulations with two independent technologies, we show that our predictions are not only accurate but also reasonably robust w.r.t. variations. Our results furthermore indicate that the exponential fitting proposed for DDM is actually only partially valid, while our analytic approach can be applied on the whole range. Even the more complex IDM is predicted reasonably accurate.},
key = {2019},
keywords = {Delay models, Glitch propagation, model parameterization, Pulse degradation},
pubstate = {published},
tppubtype = {inproceedings}
}
Delay estimation is a crucial task in digital circuit design as it provides the possibility to assure the desired functionality, but also prevents undesired behavior very early. For this purpose elaborate delay models like the Degradation Delay Model (DDM) and the Involution Delay Model (IDM) have been proposed in the past, which facilitate accurate dynamic timing analysis: Both use delay functions that determine the delay of the current input transition based on the time difference T to the previous output one. Currently, however, extensive analog simulations are necessary to determine the (parameters of the) delay function, which is a very time-consuming and cumbersome task and thus limits the applicability of these models. In this paper, we therefore thoroughly investigate the characterization procedures of a CMOS inverter on the transistor level in order to derive analytical expressions for the delay functions. Based on reasonably simple transistor models we identify three operation regions, each described by a different estimation function. Using simulations with two independent technologies, we show that our predictions are not only accurate but also reasonably robust w.r.t. variations. Our results furthermore indicate that the exponential fitting proposed for DDM is actually only partially valid, while our analytic approach can be applied on the whole range. Even the more complex IDM is predicted reasonably accurate.
Függer, M.; Maier, J.; Najvirt, R.; Nowak, T.; Schmid, U.
A faithful binary circuit model with adversarial noise Proceedings Article
In: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1327-1332, 2018, (Nominee for Best Paper Award).
@inproceedings{FMNNS18:DATE,
title = {A faithful binary circuit model with adversarial noise},
author = {M. Függer and J. Maier and R. Najvirt and T. Nowak and U. Schmid},
url = {http://burin.at/wp-content/uploads/2024/03/FMNNS18_DATE.pdf
https://arxiv.org/abs/2006.08485},
doi = {10.23919/DATE.2018.8342219},
year = {2018},
date = {2018-03-01},
urldate = {2018-03-01},
booktitle = {2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
pages = {1327-1332},
abstract = {Accurate delay models are important for static and dynamic timing analysis of digital circuits, and mandatory for formal verification. However, Függer et al. [IEEE TC 2016] proved that pure and inertial delays, which are employed for dynamic timing analysis in state-of-the-art tools like ModelSim, NC-Sim and VCS, do not yield faithful digital circuit models. Involution delays, which are based on delay functions that are mathematical involutions depending on the previous-output-to-input time offset, were introduced by Függer et al. [DATE'15] as a faithful alternative (that can easily be used with existing tools). Although involution delays were shown to predict real signal traces reasonably accurately, any model with a deterministic delay function is naturally limited in its modeling power. In this paper, we thus extend the involution model, by adding non-deterministic delay variations (random or even adversarial), and prove analytically that faithfulness is not impaired by this generalization. Albeit the amount of non-determinism must be considerably restricted to ensure this property, the result is surprising: the involution model differs from non-faithful models mainly in handling fast glitch trains, where small delay shifts have large effects. This originally suggested that adding even small variations should break the faithfulness of the model, which turned out not to be the case. Moreover, the results of our simulations also confirm that this generalized involution model has larger modeling power and, hence, applicability.},
key = {2018},
note = {Nominee for Best Paper Award},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Accurate delay models are important for static and dynamic timing analysis of digital circuits, and mandatory for formal verification. However, Függer et al. [IEEE TC 2016] proved that pure and inertial delays, which are employed for dynamic timing analysis in state-of-the-art tools like ModelSim, NC-Sim and VCS, do not yield faithful digital circuit models. Involution delays, which are based on delay functions that are mathematical involutions depending on the previous-output-to-input time offset, were introduced by Függer et al. [DATE'15] as a faithful alternative (that can easily be used with existing tools). Although involution delays were shown to predict real signal traces reasonably accurately, any model with a deterministic delay function is naturally limited in its modeling power. In this paper, we thus extend the involution model, by adding non-deterministic delay variations (random or even adversarial), and prove analytically that faithfulness is not impaired by this generalization. Albeit the amount of non-determinism must be considerably restricted to ensure this property, the result is surprising: the involution model differs from non-faithful models mainly in handling fast glitch trains, where small delay shifts have large effects. This originally suggested that adding even small variations should break the faithfulness of the model, which turned out not to be the case. Moreover, the results of our simulations also confirm that this generalized involution model has larger modeling power and, hence, applicability.
Fan, Chuchu; Meng, Yu; Maier, Jürgen; Bartocci, Ezio; Mitra, Sayan; Schmid, Ulrich
Verifying nonlinear analog and mixed-signal circuits with inputs Journal Article
In: IFAC-PapersOnLine, vol. 51, no. 16, pp. 241 - 246, 2018, ISSN: 2405-8963, (6th IFAC Conference on Analysis and Design of Hybrid Systems ADHS 2018).
@article{FMMBMS18:ADHS,
title = {Verifying nonlinear analog and mixed-signal circuits with inputs},
author = {Chuchu Fan and Yu Meng and Jürgen Maier and Ezio Bartocci and Sayan Mitra and Ulrich Schmid},
url = {http://burin.at/wp-content/uploads/2024/03/FMMBMS18_ADHS.pdf},
doi = {10.1016/j.ifacol.2018.08.041},
issn = {2405-8963},
year = {2018},
date = {2018-01-01},
urldate = {2018-01-01},
journal = {IFAC-PapersOnLine},
volume = {51},
number = {16},
pages = {241 - 246},
abstract = {We present a new technique for verifying nonlinear and hybrid models with inputs. We observe that once an input signal is fixed, the sensitivity analysis of the model can be computed much more precisely. Based on this result, we propose a new simulation-driven verification algorithm and apply it to a suite of nonlinear and hybrid models of CMOS digital circuits under different input signals. The models are low-dimensional but with highly nonlinear ODEs, with nearly hundreds of logarithmic and exponential terms. Some of our experiments analyze the metastability of bistable circuits with very sensitive ODEs and rigorously establish the connection between metastability recovery time and sensitivity.},
key = {2018},
note = {6th IFAC Conference on Analysis and Design of Hybrid Systems ADHS 2018},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
We present a new technique for verifying nonlinear and hybrid models with inputs. We observe that once an input signal is fixed, the sensitivity analysis of the model can be computed much more precisely. Based on this result, we propose a new simulation-driven verification algorithm and apply it to a suite of nonlinear and hybrid models of CMOS digital circuits under different input signals. The models are low-dimensional but with highly nonlinear ODEs, with nearly hundreds of logarithmic and exponential terms. Some of our experiments analyze the metastability of bistable circuits with very sensitive ODEs and rigorously establish the connection between metastability recovery time and sensitivity.
Maier, Jürgen
Modeling the CMOS Inverter using Hybrid Systems Technical Report
E182 - Institut für Technische Informatik; Technische Universität Wien no. TUW-259633, 2017.
BibTeX |
@techreport{M17:TR,
title = {Modeling the CMOS Inverter using Hybrid Systems},
author = {Jürgen Maier},
url = {http://publik.tuwien.ac.at/files/publik_259633.pdf},
year = {2017},
date = {2017-01-01},
urldate = {2017-01-01},
number = {TUW-259633},
institution = {E182 - Institut für Technische Informatik; Technische Universität Wien},
key = {2017},
keywords = {},
pubstate = {published},
tppubtype = {techreport}
}
Steininger, Andreas; Maier, Jürgen; Najvirt, Robert
The Metastable Behavior of a Schmitt-Trigger Proceedings Article
In: 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 57-64, 2016.
@inproceedings{7584893,
title = {The Metastable Behavior of a Schmitt-Trigger},
author = {Andreas Steininger and Jürgen Maier and Robert Najvirt},
url = {http://burin.at/wp-content/uploads/2024/03/SMN16_ASYNC.pdf},
doi = {10.1109/ASYNC.2016.19},
year = {2016},
date = {2016-01-01},
urldate = {2016-01-01},
booktitle = {2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)},
pages = {57-64},
abstract = {Schmitt-Trigger circuits are the method of choice for converting general signal shapes into clean, well-behaved digital ones. In this context these circuits are often used for metastability handling, as well. However, like any other positive feedback circuit, a Schmitt-Trigger can become metastable itself. Therefore, its own metastable behavior must be well understood, in particular the conditions that may cause its metastability. In this paper we will build on existing results from Marino to show that (a) a monotonic input signal can cause late transitions but never leads to a non-digital voltage at the Schmitt-Trigger output, and (b) a non-monotonic input can pin the Schmitt-Trigger output to a constant voltage at any desired (also non-digital) level for an arbitrary duration. In fact, the output can even be driven to any waveform within the dynamic limits of the system. We will base our analysis on a mathematical model of a Schmitt-Trigger's dynamic behavior and perform SPICE simulations to support our theory and confirm its validity for modern CMOS implementations. Furthermore, we will discuss several use cases of a Schmitt-Trigger in the light of our results.},
keywords = {Integrated circuit modeling;Feedback circuits;Hysteresis;Threshold voltage;Negative feedback;Mathematical model;Context;Schmitt-Trigger;Metastability;Asynchronous;Positive Feedback Circuit;Glitch;Late Transition},
pubstate = {published},
tppubtype = {inproceedings}
}
Schmitt-Trigger circuits are the method of choice for converting general signal shapes into clean, well-behaved digital ones. In this context these circuits are often used for metastability handling, as well. However, like any other positive feedback circuit, a Schmitt-Trigger can become metastable itself. Therefore, its own metastable behavior must be well understood, in particular the conditions that may cause its metastability. In this paper we will build on existing results from Marino to show that (a) a monotonic input signal can cause late transitions but never leads to a non-digital voltage at the Schmitt-Trigger output, and (b) a non-monotonic input can pin the Schmitt-Trigger output to a constant voltage at any desired (also non-digital) level for an arbitrary duration. In fact, the output can even be driven to any waveform within the dynamic limits of the system. We will base our analysis on a mathematical model of a Schmitt-Trigger's dynamic behavior and perform SPICE simulations to support our theory and confirm its validity for modern CMOS implementations. Furthermore, we will discuss several use cases of a Schmitt-Trigger in the light of our results.
Steininger, A.; Maier, J.; Najvirt, R.
The Metastable Behavior of a Schmitt-Trigger Proceedings Article
In: 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 57-64, 2016.
@inproceedings{SMN16:ASYNC,
title = {The Metastable Behavior of a Schmitt-Trigger},
author = {A. Steininger and J. Maier and R. Najvirt},
url = {http://burin.at/wp-content/uploads/2024/03/SMN16_ASYNC.pdf
https://arxiv.org/abs/2006.08319},
doi = {10.1109/ASYNC.2016.19},
year = {2016},
date = {2016-05-01},
urldate = {2016-05-01},
booktitle = {2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)},
pages = {57-64},
abstract = {Schmitt-Trigger circuits are the method of choice for converting general signal shapes into clean, well-behaved digital ones. In this context these circuits are often used for metastability handling, as well. However, like any other positive feedback circuit, a Schmitt-Trigger can become metastable itself. Therefore, its own metastable behavior must be well understood, in particular the conditions that may cause its metastability. In this paper we will build on existing results from Marino to show that (a) a monotonic input signal can cause late transitions but never leads to a non-digital voltage at the Schmitt-Trigger output, and (b) a non-monotonic input can pin the Schmitt-Trigger output to a constant voltage at any desired (also non-digital) level for an arbitrary duration. In fact, the output can even be driven to any waveform within the dynamic limits of the system. We will base our analysis on a mathematical model of a Schmitt-Trigger's dynamic behavior and perform SPICE simulations to support our theory and confirm its validity for modern CMOS implementations. Furthermore, we will discuss several use cases of a Schmitt-Trigger in the light of our results.},
key = {2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Schmitt-Trigger circuits are the method of choice for converting general signal shapes into clean, well-behaved digital ones. In this context these circuits are often used for metastability handling, as well. However, like any other positive feedback circuit, a Schmitt-Trigger can become metastable itself. Therefore, its own metastable behavior must be well understood, in particular the conditions that may cause its metastability. In this paper we will build on existing results from Marino to show that (a) a monotonic input signal can cause late transitions but never leads to a non-digital voltage at the Schmitt-Trigger output, and (b) a non-monotonic input can pin the Schmitt-Trigger output to a constant voltage at any desired (also non-digital) level for an arbitrary duration. In fact, the output can even be driven to any waveform within the dynamic limits of the system. We will base our analysis on a mathematical model of a Schmitt-Trigger's dynamic behavior and perform SPICE simulations to support our theory and confirm its validity for modern CMOS implementations. Furthermore, we will discuss several use cases of a Schmitt-Trigger in the light of our results.
Steininger, A.; Najvirt, R.; Maier, J.
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? Proceedings Article
In: 2016 Euromicro Conference on Digital System Design (DSD), pp. 372-379, 2016.
@inproceedings{SNM16:DSD,
title = {Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?},
author = {A. Steininger and R. Najvirt and J. Maier},
url = {http://burin.at/wp-content/uploads/2024/03/SNM16_DSD.pdf
https://arxiv.org/abs/2006.08415},
doi = {10.1109/DSD.2016.56},
year = {2016},
date = {2016-08-01},
urldate = {2016-08-01},
booktitle = {2016 Euromicro Conference on Digital System Design (DSD)},
pages = {372-379},
abstract = {Schmitt-Trigger stages are the method of choice for robust discretization of input voltages with excessive transition times or significant noise. However, they may suffer from metastability. Based on the experience that the cascading of flip-flop stages yields a dramatic improvement of their overall metastability hardness, in this paper we elaborate on the question whether the cascading of Schmitt-Trigger stages can obtain a similar gain. We perform a theoretic analysis that is backed up by an existing metastability model for a single Schmitt-Trigger stage and elaborate some claims about the behavior of a Schmitt-Trigger cascade. These claims suggest that the occurrence of metastability is indeed reduced from the first stage to the second which suggests an improvement. On the downside, however, it becomes clear that metastability can still not be completely ruled out, and in some cases the behavior of the cascade may be less beneficial for a given application, e.g. by introducing seemingly acausal transitions. We validate our findings by extensive HSPICE simulations in which we directly cover our most important claims.},
key = {2016},
keywords = {Clocks;Hysteresis;Latches;Mathematical model;Robustness;Synchronization;Threshold voltage;Hysteresis;Metastability;Schmitt-Trigger cascade},
pubstate = {published},
tppubtype = {inproceedings}
}
Schmitt-Trigger stages are the method of choice for robust discretization of input voltages with excessive transition times or significant noise. However, they may suffer from metastability. Based on the experience that the cascading of flip-flop stages yields a dramatic improvement of their overall metastability hardness, in this paper we elaborate on the question whether the cascading of Schmitt-Trigger stages can obtain a similar gain. We perform a theoretic analysis that is backed up by an existing metastability model for a single Schmitt-Trigger stage and elaborate some claims about the behavior of a Schmitt-Trigger cascade. These claims suggest that the occurrence of metastability is indeed reduced from the first stage to the second which suggests an improvement. On the downside, however, it becomes clear that metastability can still not be completely ruled out, and in some cases the behavior of the cascade may be less beneficial for a given application, e.g. by introducing seemingly acausal transitions. We validate our findings by extensive HSPICE simulations in which we directly cover our most important claims.
Maier, Jürgen
Modeling III-V Semiconductor Interfaces at an Atomistic Level using Empirical Potentials Masters Thesis
TU Wien, Vienna, Austria, 2016, (Master Thesis, Institute of Solid State Electronics, TU Wien, Vienna, Austria).
@mastersthesis{M16:MSC,
title = {Modeling III-V Semiconductor Interfaces at an Atomistic Level using Empirical Potentials},
author = {Jürgen Maier},
url = {http://catalogplus.tuwien.ac.at/UTW:UTW:UTW_alma2150179390003336},
year = {2016},
date = {2016-04-01},
urldate = {2016-04-01},
school = {TU Wien, Vienna, Austria},
abstract = {III-V semiconductor heterostructures provide a solid basis for electronic and optoelectronic devices beyond conventional silicon-based CMOS technology and have therefore been the subject of thorough investigations in the past. Very detailed information have been achieved so far regarding the properties of single materials, however interfaces were assumed to be ideal and therfore neglected in most models. Such simplifications can not be justified any more since it was already shown that interface roughness influences the electronic characteristics of devices. Furthermore, increasing complexity and shrinking feature size will push the importance of interfaces in the future even further. This work provides therefore a detailed introduction on methods to model interfaces between III-V semiconductor materials using empirical potentials. The latter provide an efficient way to model chemical bonds and therefore the structural description of multi-layer structures. Compared to other approaches, which commonly describe the material properties in a continuum approach, empirical interaction potentials can be used to thoroughly model the crystalline structure, as well as potential local variations in the material composition and resulting strain. The main topic of this thesis was the development of an algorithm to generate interface configurations, which are optimized with respect to their total energy. These procedures therby try to imitate growth processes observed in nature as closely as possible to achieve physical reasonable solution. Interfacial structures are first created at the basis of an ideal lattice and then allowed to relax using Metropolis Monte Carlo methods, which gives each atom the oportunity to find its energetically optimal location inside the crystal. Within a final step, not only the total energy but also local strain of individual bonds are analyzed to gain insight into the electronic behavior at interfaces. This alogrithm was ultimately used to derive detailed results for the technologically relevant material systems GaSb/InAs, AlSb/InAs and InGaAs/InAlAs, whereat the power of the Vienna Scientific Cluster was utilized.},
note = {Master Thesis, Institute of Solid State Electronics, TU Wien, Vienna,
Austria},
keywords = {},
pubstate = {published},
tppubtype = {mastersthesis}
}
III-V semiconductor heterostructures provide a solid basis for electronic and optoelectronic devices beyond conventional silicon-based CMOS technology and have therefore been the subject of thorough investigations in the past. Very detailed information have been achieved so far regarding the properties of single materials, however interfaces were assumed to be ideal and therfore neglected in most models. Such simplifications can not be justified any more since it was already shown that interface roughness influences the electronic characteristics of devices. Furthermore, increasing complexity and shrinking feature size will push the importance of interfaces in the future even further. This work provides therefore a detailed introduction on methods to model interfaces between III-V semiconductor materials using empirical potentials. The latter provide an efficient way to model chemical bonds and therefore the structural description of multi-layer structures. Compared to other approaches, which commonly describe the material properties in a continuum approach, empirical interaction potentials can be used to thoroughly model the crystalline structure, as well as potential local variations in the material composition and resulting strain. The main topic of this thesis was the development of an algorithm to generate interface configurations, which are optimized with respect to their total energy. These procedures therby try to imitate growth processes observed in nature as closely as possible to achieve physical reasonable solution. Interfacial structures are first created at the basis of an ideal lattice and then allowed to relax using Metropolis Monte Carlo methods, which gives each atom the oportunity to find its energetically optimal location inside the crystal. Within a final step, not only the total energy but also local strain of individual bonds are analyzed to gain insight into the electronic behavior at interfaces. This alogrithm was ultimately used to derive detailed results for the technologically relevant material systems GaSb/InAs, AlSb/InAs and InGaAs/InAlAs, whereat the power of the Vienna Scientific Cluster was utilized.
Maier, Jürgen; Detz, Hermann
Atomistic modeling of interfaces in III-V semiconductor superlattices Journal Article Open Access
In: physica status solidi (b), vol. 253, no. 4, pp. 613–622, 2016, ISSN: 1521-3951.
@article{MD16:PSSB,
title = {Atomistic modeling of interfaces in III-V semiconductor superlattices},
author = {Jürgen Maier and Hermann Detz},
url = {http://burin.at/wp-content/uploads/2024/04/MD16_PSSB.pdf},
doi = {10.1002/pssb.201552496},
issn = {1521-3951},
year = {2016},
date = {2016-01-01},
urldate = {2016-01-01},
journal = {physica status solidi (b)},
volume = {253},
number = {4},
pages = {613–622},
abstract = {Semiconductor heterostructures are well characterized experimentally and provide a solid basis for electronic and optoelectronic devices ranging from single interface to complex superlattice structures. Yet, structural and electronic models commonly describe the material properties in a continuum approach, which neglects the crystalline structure, as well as potential local variations of the composition and resulting strain. Empirical interaction potentials provide an efficient way to model chemical bonds and therefore allow a structural description of multi-layer structures. This work provides a detailed introduction on methods to minimize the total energy of semiconductor heterostructures at an atomistic level. We present an algorithm to minimize the total energy and generate optimized interface configurations. The relaxed structures are then evaluated with respect to interfacial strain, where different strain calculation methods are evaluated and compared with experimental data.},
key = {2016},
keywords = {atomistic modeling, III-V semiconductors, interfaces, OpenAccess, roughness, superlattices},
pubstate = {published},
tppubtype = {article}
}
Semiconductor heterostructures are well characterized experimentally and provide a solid basis for electronic and optoelectronic devices ranging from single interface to complex superlattice structures. Yet, structural and electronic models commonly describe the material properties in a continuum approach, which neglects the crystalline structure, as well as potential local variations of the composition and resulting strain. Empirical interaction potentials provide an efficient way to model chemical bonds and therefore allow a structural description of multi-layer structures. This work provides a detailed introduction on methods to minimize the total energy of semiconductor heterostructures at an atomistic level. We present an algorithm to minimize the total energy and generate optimized interface configurations. The relaxed structures are then evaluated with respect to interfacial strain, where different strain calculation methods are evaluated and compared with experimental data.
Maier, J.; Detz, H.; Strasser, G.
Atomistic Modeling of III-V Semiconductor Interfaces Proceedings Article
In: Vienna Young Scientist Symposium, pp. 38-39, 2015.
@inproceedings{MDS15:VSS,
title = {Atomistic Modeling of III-V Semiconductor Interfaces},
author = {J. Maier and H. Detz and G. Strasser},
year = {2015},
date = {2015-06-01},
booktitle = {Vienna Young Scientist Symposium},
pages = {38-39},
key = {2015},
keywords = {atomistic modeling, III-V semiconductors},
pubstate = {published},
tppubtype = {inproceedings}
}
Detz, H.; Maier, J.; Strasser, G.
Atomistic Modeling of Interfacial Strain in III-V Heterostructures Proceedings Article
In: 2015 Compound Semiconductor Week, pp. 1-2, 2015.
@inproceedings{DMS15:CSW,
title = {Atomistic Modeling of Interfacial Strain in III-V Heterostructures},
author = {H. Detz and J. Maier and G. Strasser},
year = {2015},
date = {2015-06-01},
booktitle = {2015 Compound Semiconductor Week},
pages = {1-2},
key = {2015},
keywords = {atomistic modeling, III-V semiconductors},
pubstate = {published},
tppubtype = {inproceedings}
}
Maier, J.; Steininger, A.
Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic Proceedings Article
In: Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pp. 33-38, 2014.
@inproceedings{MS14:DDECS,
title = {Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic},
author = {J. Maier and A. Steininger},
url = {http://burin.at/wp-content/uploads/2024/03/MS14_DDECS.pdf
https://arxiv.org/abs/2006.04577},
doi = {10.1109/DDECS.2014.6868759},
year = {2014},
date = {2014-04-01},
urldate = {2014-04-01},
booktitle = {Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on},
pages = {33-38},
abstract = {Complementing concurrent checking with online testing is crucial for preventing fault accumulation in fault-tolerant systems with long mission times. While implementing a non-intrusive online test is cumbersome in a synchronous environment, this task becomes even more challenging in asynchronous designs. The latter receive increasing attention, mainly due to their elastic timing behaviour; however the issues related with their testing remain a key obstacle for their wide adoption. In this paper we present a novel approach for testing of asynchronous circuits that leverages the redundancy present in the conventional 4-phase protocol for implementing a fully transparent and fully concurrent test procedure. The key idea is to use the protocol's unproductive NULL phase for processing test vectors, thus effectively interleaving the incoming 4-phase data stream with a test data stream in a 2-phase fashion. We present implementation templates for the fundamental building blocks required and give a proof-of-concept by an example application that also serves as a platform for evaluating the overheads of our solution which turn out to be moderate.},
key = {2014},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Complementing concurrent checking with online testing is crucial for preventing fault accumulation in fault-tolerant systems with long mission times. While implementing a non-intrusive online test is cumbersome in a synchronous environment, this task becomes even more challenging in asynchronous designs. The latter receive increasing attention, mainly due to their elastic timing behaviour; however the issues related with their testing remain a key obstacle for their wide adoption. In this paper we present a novel approach for testing of asynchronous circuits that leverages the redundancy present in the conventional 4-phase protocol for implementing a fully transparent and fully concurrent test procedure. The key idea is to use the protocol's unproductive NULL phase for processing test vectors, thus effectively interleaving the incoming 4-phase data stream with a test data stream in a 2-phase fashion. We present implementation templates for the fundamental building blocks required and give a proof-of-concept by an example application that also serves as a platform for evaluating the overheads of our solution which turn out to be moderate.
Maier, Jürgen
Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic Masters Thesis
TU Wien, Vienna, Austria, 2014, (Master Thesis, Institute of Computer Engineering, TU Wien, Vienna, Austria).
BibTeX |
@mastersthesis{M14:MSC,
title = {Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST)
Approach for Asynchronous Logic},
author = {Jürgen Maier},
url = {http://catalogplus.tuwien.ac.at/UTW:UTW:UTW_alma2139475450003336},
year = {2014},
date = {2014-10-01},
school = {TU Wien, Vienna, Austria},
note = {Master Thesis, Institute of Computer Engineering, TU Wien, Vienna, Austria},
keywords = {},
pubstate = {published},
tppubtype = {mastersthesis}
}